In recent years, with high integration and high functionality of a semiconductor integrated circuit, the development of microfabrication technology for miniaturization and density growth of a semiconductor element is advancing. In the manufacturing of a semiconductor integrated circuit device (hereinafter also referred to as a “semiconductor device”), in order to prevent the problem such that unevenness (difference in level) of the surface of a layer exceeds depth of focus of lithography and sufficient resolution is not obtained, it is conventionally performed to flatten an interlayer insulating film, an embedding wiring and the like using chemical mechanical polishing (hereinafter referred to as “CMP”). Importance of high flattening by CMP is increasing with severer requirements of high definition and miniaturization of an element.
Furthermore, in recent years, in the manufacturing of a semiconductor device, an isolation method by shallow trench having small element isolation width (Shallow Trench Isolation; hereinafter referred to as “STI”) is introduced in order to proceed with higher miniaturization of a semiconductor element.
The STI is a technique for forming an electrically insulated element region by forming a trench (groove) on a silicon substrate and embedding an insulating film in the trench. In the STI, as shown in FIG. 1A, an element region of a silicon substrate 1 is masked with a silicon nitride film 2 or the like, a trench 3 is formed on the silicon substrate 1, and an insulating film such as a silicon dioxide film 4 is then deposited so as to embed the trench 3. The silicon dioxide film 4 on the silicon nitride film 2 as a convex part is polished and removed by CMP while remaining the silicon dioxide film 4 in the trench 3 as a concave part. Thus, an element isolation structure having the silicon dioxide film 4 embedded in the trench 3 is obtained as shown in FIG. 1B.
In CMP in the STI, the progress of polishing can be stopped at the time when a silicon nitride film has been exposed, by increasing a selection ratio between a silicon dioxide film and a silicon nitride film (the selection ratio means a ratio between a removal rate of the silicon dioxide film and a removal rate of the silicon nitride film, and is hereinafter also simply referred to as a “selection ratio”). In a polishing method using a silicon nitride film as a stopper film, smoother surface can be obtained as compared with the ordinary polishing method.
In CMP technology in recent years, not only high removal rate to a silicon dioxide film is required from the standpoint of cost, but also height of the selection ratio described above is becoming important.
A method for improving polishing characteristics of a polishing agent is conventionally proposed. Patent Document 1 discloses a polishing agent containing cerium oxide particles as abrasives, and an amine such as aliphatic amine and heterocyclic amine, or a carboxylic acid such as aminocarboxylic acid, cyclic monocarboxylic acid and unsaturated monocarboxylic acid.
However, in the polishing agent disclosed in Patent Document 1, high value is secured to a certain degree in a removal rate of a silicon dioxide film, but the suppression of a removal rate of a silicon nitride film is not sufficient. Therefore, it did not say that the selection ratio between a silicon dioxide film and a silicon nitride film is sufficiently high. For this reason, flatness of polishing was not sufficient.
Patent Document 1: JP-T-2006-520530 (WO2004/069947)